典型文献
Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor
文献摘要:
We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate.The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps.The position depth of the traps in the oxide from Si/SiO2 interface is 0.35 nm,calculated by utilizing the dependence of the capture and emission time on the gate voltage.Moreover,by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simula-tion software,we achieved the trap density of 1.9 x 1012 cm-2 and the energy level position of traps at 0.18 eV below the intrins-ic Fermi level.
文献关键词:
中图分类号:
作者姓名:
Yifan Fu;Liuhong Ma;Zhiyong Duan;Weihua Han
作者机构:
School of Physics and Microelectronics,Zhengzhou University,Zhengzhou 450001,China;Engineering Research Center for Semiconductor Integrated Technology,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;Center of Materials Science and Optoelectronics Engineering,University of Chinese Academy of Sciences,Beijing 100083,China;Institute of Intelligence Sensing in Zhengzhou University,Zhengzhou 450001,China
文献出处:
引用格式:
[1]Yifan Fu;Liuhong Ma;Zhiyong Duan;Weihua Han-.Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor)[J].半导体学报(英文版),2022(05):81-85
A类:
junctionless,telegraph,intrins
B类:
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AB值:
0.550183
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