典型文献
An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
文献摘要：
We present a new counter-based Wallace-tree(CBW)8×8 multiplier.The multiplier's counters are implemented with a new hybrid full adder(FA)cell,which is based on the transmission gate(TG)technique.The proposed FA,TG-based AND gate,and hybrid half adder(HA)generate M∶3(4≤M≤7)digital counters with the ability to save at least 50％area occupation.Simulations by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art designs.By using the proposed cells,the CBW multiplier exhibits high driving capability,low power consumption,and high speed.The CBW multiplier has a 0.0147 mm2 die area in a pad.The post-layout extraction proves the accuracy of experimental implementation.An image blending mechanism is proposed,in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing applications.The peak signal-to-noise ratio(PSNR)and structural similarity index metric(SSIM)are calculated as image quality parameters,and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.
文献关键词：
中图分类号：
作者姓名：
Ayoub SADEGHI;Nabiollah SHIRI;Mahmood RAFIEE;Mahsa TAHGHIGH
作者机构：
Department of Electrical Engineering,Shiraz Branch,Islamic Azad University,Shiraz 71987-74731,Iran
文献出处：
引用格式：
[1]Ayoub SADEGHI;Nabiollah SHIRI;Mahmood RAFIEE;Mahsa TAHGHIGH-.An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending)[J].信息与电子工程前沿（英文）,2022(06):950-965
A类：
adder
B类：
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AB值：
0.505986
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