典型文献
TLP-LDPC:Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis
文献摘要：
Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to real-world noises.Fast prototyping field-programmable gate array(FPGA)-based decoder is essential to achieve high decoding performance while accelerating the development process.This paper proposes a three-level parallel architecture,TLP-LDPC,to achieve high throughput by fully exploiting the characteristics of both LDPC and underlying hardware while effectively scaling to large-size FPGA platforms.The three-level parallel architecture contains a low-level decoding unit,a mid-level multi-unit decoding core,and a high-level multi-core decoder.The low-level decoding unit is a basic LDPC computation component that effectively combines the features of the LDPC algorithm and hardware with the specific structure(e.g.,Look-Up-Table,LUT)of the FPGA and eliminates potential data conflicts.The mid-level decoding core integrates the input/output and multiple decoding units in a well-balancing pipelined fashion.The top-level multi-core architecture conveniently makes full use of board-level resources to improve the overall throughput.We develop an LDPC C++code with dedicated pragmas and leverage HLS tools to implement the TLP-LDPC architecture.Experimental results show that TLP-LDPC achieves 9.63 Gbps end-to-end decoding throughput on a Xilinx Alveo U50 platform,3.9x higher than existing HLS-based FPGA implementations.
文献关键词：
中图分类号：
作者姓名：
Yi-Fan Zhang;Lei Sun;Qiang Cao
作者机构：
Wuhan National Laboratory for Optoelectronics,Wuhan 430074,China
文献出处：
引用格式：
[1]Yi-Fan Zhang;Lei Sun;Qiang Cao-.TLP-LDPC:Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis)[J].计算机科学技术学报（英文版）,2022(06):1290-1306
A类：
Prototyping,heck,C++code,pragmas,Alveo
B类：
TLP,LDPC,Three,Level,Parallel,FPGA,Architecture,Fast,Decoder,Using,High,Synthesis,Low,Density,Parity,Codes,excellent,error,correction,capabilities,have,been,widely,used,both,data,communication,storage,fields,construct,reliable,cyber,physical,systems,that,resilient,real,world,noises,prototyping,programmable,gate,array,decoder,essential,decoding,performance,while,accelerating,development,process,This,paper,proposes,three,level,parallel,architecture,throughput,by,fully,exploiting,characteristics,underlying,hardware,effectively,scaling,large,size,platforms,contains,low,mid,core,basic,computation,component,combines,features,algorithm,specific,structure,Look,Up,Table,LUT,eliminates,potential,conflicts,integrates,input,output,multiple,units,well,balancing,pipelined,fashion,top,conveniently,makes,board,resources,improve,overall,We,dedicated,leverage,HLS,tools,Experimental,results,show,achieves,Gbps,end,Xilinx,U50,9x,higher,than,existing,implementations
AB值：
0.554481
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